Silicon ensemble issue

Discussion in 'Cadence' started by Jerome, Jun 23, 2006.

  1. Jerome

    Jerome Guest

    Hi all,

    A very stupid issue. With a new technology i use i can not complete a
    routing without generating 1000000 errors. The errors are DRC errors on
    each metal layers. I assume it is due to the via shapes that are
    rectangulars (not squared). So my question is: How are calculated the
    GCELLS for the routing?
    In my lef file i have:

    WIDTH 0.1
    SPACING 0.1
    PITCH 0.3
    OFFSET 0.15

    it seems that the channels used by SE make 0.2um instead of 0.3um.

    So the second question is :
    The GCELL is built with WIDTH + SPACING or with PITCH?
    On my opinion, it should be PITCH.

    Thanks in advance.
    jerome.
     
    Jerome, Jun 23, 2006
    #1
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