seperating power grid

I have the standard-cell based layout (GDS II) and I am interested in
seperating its power grid. Basically I need to analyze the power grid
seperately. Can someone suggest how I can separate the power/ground
grid as a seperate layout?

Thanks
Saby.

 

Not sure what you mean.
Inherently the Power/Ground grid is connected to the circuit.

However you decide to disconnect it introduces some inaccuracies that I
cannot argue about.

I was once given the challenge of ( in a pure CMOS FLOW ) adding a CML
library with some significant
tail currents in the switching logic. The "powers that be" (tm) decided that
the "power supply" should not drop more than
150mv during normal operation. We were told to assume that the spec sheets
for the CML logic cells told us the DC power
and the operation of switching should not add any significant power as we
were just switching tail currents to different legs.
( to a first order )

My problem was to take this cell library and to some power grid analysis.
( note that this was ~ 15 years ago ... )
What I did was to create "power" views of each cell that had copied the
power/ground pins from an extracted rep and
added a DC current source that was set based on the spec sheet of each cell.
This First attempt failed due to the fact that all of the VDD! pins of each
cell shorted to the VDD! global net and lost the
parasitic R. ( so ditched global VDD! for local VDD .... ) Also the cells
had VDD pins that covered the whole top edge
of the cell ( and pins are perfect conductors... argh ... ) ... so in the
power views the pins were reduced to 2unitsX2units at
the center of the initial pin.

Then with careful setup and use of alarms in spectre ... we could show what
the I/R drop (in the DC sense) would be to the CML cells.

This enabled us to redesign the widths of these supplies where needed.

-- Gerry

 

Actually I am also interested in doing power grid analysis for smiliar
purpose as you mentioned. I want to seperate the 3-4 layer metal
power/ground grid and simulate that seperately for studying the IR
drop etc.

-saby

 

I had the same problem, and unfortunately i could not find a simple
answer. The "problem" with Assura is that it does not allow 2 net names
on the same net i.e. you can delete cells from layout and leave only
power and gnd lines but you cant "name" the places on pwr/gnd lines
where this cells connect to, because the whole PWR or GND net is
already named...

I have used "dummy" cells in layout instead of "real" ones, and then I
have deleted them manually from netlist after RC extraction. This was
the only solution I could think of...

If you find a better solution, please let me know

Regards,
Emilio

 

Hmmm.. I wonder if any other tool (like Calibre xRC) can do that?

 

My solution ( but I was also a kit developer ... ) was to create PSEUDO
LAYERS

(REALLY ALL CONDUCTORS WITH A PURPOSE OF "r" )

and I created the schematic equivalents ( to keep LVS happy )
and then I would not have to manage 2 layouts ....

But ( Hello Cadence ... ) they manage to complicate the introduction
of scoped global ( they call in "Inherited connections ) and made it almost
unusable.

I was able to get several design kits created without any global powers and
was able to create an extensive set of tools to deal with supply impedance.

( see 1995 paper at CUG on "Substrate Aware Verification" )

But kit manipulation is not for the faint of heart.

YMMV

--- Gerry

p.s. Also added "Z" and "L" layers as hooks into 3d extract, T-line and
Inductor, X-fomer & Balun modeling ...
only for extreme use (say +20gig edge rates or analog frequencies ... )