sedsm ctgen hierarchy problem

Hello,

We've been trying to improve our clock tree generation since it bit us
on
our last tapeout and limited our clock speed. We're to the point now
where
we have primetime/syn2tlf generate a .tlf for our macro blocks. At the
top
level, we need to specify the insertion delays for the clock tree in
each
macro block so it can balanace from the top level clk root to macro
block gates.

information into the tlf. primetime doesn't appear to want to do that.
It's writing out 0's for the clk tree delays. The second method is to
specify each block's clock's min and max insertion delay in the ctgen

constraints file. The same place you specifiy the top level clock tree
requirements. These are mutually exclusive options according to the
manuals.

When I try to do this second option, ctgen then croaks trying to read
the
(unchanged) tlfs. I get:

#---{22:33:43 * clockRoute : Extract Lpin insertion delay: begin}
#---{22:33:44 tcuWarning: Incompatible format in ctlf library
'/wims/apr/tlf/dsp.tlf'.}
#---{22:33:44 Reading timing library "/wims/apr/tlf/dsp.tlf" ...}
#---{22:33:44 *ERROR* Unable to read timing library file
/wims/apr/tlf/dsp.tlf.}
#---{22:33:44 * clockRoute : Extract Lpin insertion delay: end }

I have no problems running ctgen with no insertion delay commands in
either
the tlfs or ctgen constraints files.

So then I tried manually adding Insertion_Delay() statements into the
tlfs
with or without the set_insertion_delays statements in the ctgen
constraints. I get the same error either way. I'm following syntax
exactly
as it is in the cadence ctgen and tlf manuals.

We're using cadence-dsme-5.4 and a combination of version 3.1 tlfs for

macros and 4.1 tlfs for std cells/memories.

Any help would be greatly appreciated.
Eric