Hi, If I generate an sdf file with design_analyzer or primetime 1) when I only import the .db library and the verilog gate level netlist I get the same delays as when I do 1) + I read in the dspf parasitics file. What do I do wrong? Do I need to execute a commando after I do read_parasitics in primetime or set_load in design_analyzer? Is it necessary to define the clk and the delay on the in/output signals? KRis
