schematic from Verilog

Discussion in 'Cadence' started by Kamal, Aug 8, 2008.

  1. Kamal

    Kamal Guest

    I am using Verilog In to generate a schematic. However, the schematic
    has all the blocks connected with wires going from pin to pin. Is
    there a way that we can create a schematic with some defined wire
    length coming out of each instance and just labels attached to each
    net.

    This way my schematic would look much cleaner (due to absence of nets
    crossing each other) and still clean as everything is connected by
    name.

    Thanks,
    Kamal
     
    Kamal, Aug 8, 2008
    #1
  2. Kamal

    S. Badel Guest

    I think you just have to disable the "Full Place and Route" option. Or something along these lines...

    Cheers,
    Stéphane
     
    S. Badel, Aug 14, 2008
    #2
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