Run Verilog-XL error in IC5.0

Discussion in 'Cadence' started by BL, May 21, 2004.

  1. BL

    BL Guest

    Hi, when i verify the functionality of the schematic of using
    VERILOG-XL in IC5.0, STAER interactive that shown:

    WARNING : VLOGIF [BADFILE GLOBAL]
    user-settable global variable : verilog SimBinary is invalid, Relative
    pathnames are relative to run directory OK / CANCEL abort simulation.

    Simulation option warning:
    Invalid verilog executable verilog
    Please check existance and/or permissions and try again. Relative
    pathnames are relative to run directory.

    i check the license in CIW "virtuoso schematic composer verilog
    interface" is running.

    Please help me to solve it.

    Thank you
    benny
     
    BL, May 21, 2004
    #1
  2. BL

    Andrew Beckett Guest

    Do you have an LDV installation (e.g. LDV51), and have your UNIX path to
    include the <ldvInstDir>/tools/bin ?

    "verilog" is not contained within the IC50 hierarchy, and so you need an LDV
    stream installed and in your path to be able to access it.

    Regards,

    Andrew.

     
    Andrew Beckett, May 25, 2004
    #2
  3. BL

    BL Guest

    Thank you. I do not have installed LDV in linux. Despite
    "verilog-XL", any other software not include in IC5.0 ?

    Regards,
    Benny


     
    BL, May 27, 2004
    #3
  4. BL

    Andrew Beckett Guest

    Verilog hasn't been in the IC stream since IC443 (IC443 was the last version it
    was still there for; it wasn't there in IC445 nor IC446).

    So this is nothing new. There was this effort to split out tools into
    separate streams, and to avoid duplication where possible - but that was
    several releases ago now.

    leapfrog is also not in IC50 because it was end of lifed some time ago.

    Andrew.

     
    Andrew Beckett, May 27, 2004
    #4
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