RTL netlist icfb import issue

Hi,

I am facing a weird issue when importing a gate level verilog netlist
in cadence icfb.

In my RTL code I have a module with one of them having a carry in
stuck to 1'b0.
I synthesize with Design Compiler and in the RTL I can see the input
module having 1'b0 and a lot of other gates having also 1'b0 as input
gate...

When I import in icfb, the LVS is clean, no issue..

But if I put this schematic in a hierarchy, the LVS on the cleaned
module doesn't match...

I can see in the schematic a gnd !* on the first gate of the input
module but with diffrent properties than the gates having also the
same gnd !* on the net
That cause a N0 net shorted to GND in LVS comparison

My only response to this issue is to put an input pin to my layout
receiving a GND going to my module as a signal !!!... not very nice...

Is there a way to avoid this issue ?

It seems cadence thinks it's a kind of power pin because it's a 0V
connected a module input pin... I don't know right know exactly what's
going on...