RTL-Compiler [read in the Netlist]

How can I read in a veriolg Netlist into the RTL-Compiler?

Actually, I'd like to read a Netlist, which contain timing information
as well (something like a *.db file).

How can I do so?

 

If the RTL-compiler you are referring is simulation tool like VCS or
verilog-xl, you can use $sdf_annotate task in your test bench. SDF file
has the timing information.
Or, if you only want to find out delay of a cell or between cells, you
can try GOF, Gates-On-the-Fly from NanDigits.
GOF can load netlist with SDF file, and you can check timing
information when browser the netlist.
A link is here
http://www.nandigits.com/sdf_timing.htm

Nandy
www.nandigits.com
Netlist Debug/ECO in GUI mode

 

I only want to know how to read a Netlist inside the RTL-Compiler. I
need an exact command.

 

It seems the 'read_hdl -v2001' command is used to read a RTL code, not
a Netlist

Actually, I need to read the Netlist...

 

It seems the "read_hdl -v2001" command is used to read a RTL code, not
a Netlist

I need to read a Netlist...

 

So you tried it and it didn't work ?

If you have the definitions of the gates either through a library or a
set of modules, there is no difference.

 

read_hdl -structural

for 5.2

read_netlist

 

Thanks, I'll try it