Rewire shematics SKill code

Hi,

I am converting a schematic from one technology to another. The
symbols are a little smaller in the new technology so existing wires
will have opens to some symbols.

Does anyone have any Skill code for rewiring short segments of wire
in a schematic when symbol sizes change?

Thanks.

 

Hi Mike,

I don't have anything lying around, but it ought to be quite straightforward
using the schCreateWire function. If you collect the pin locations before
you replace the component, and the new pin locations afterwards, it
shouldn't be that hard to implement.

Regards,

Andrew.

 

Mike:
I am in the exact same position as you. I was thinking that I would
add a wire with dbCreateLine. The following adds a wire when the
instID->orient = "R0":

dbCreateLine(cv list("wire" "drawing") list(list(newx newy-0.375)
list(newx newy-0.5)))

One needs to handle all the rotation cases and all have cases for 2
terminal, 3 terminal, ... devices. Any ideas on a more elegant
solution would be most welcome.

My original thought was that I would just move the device after
translation. That is, the device would become smaller so I would just
shift it up to connect to the net again but there is no way in skill
to move the instance and have the wire connected to the terminal go
with. At least I couldn't find it.

 

Erik,

See my other append, but the answer to your last question will be
schStretch() - not currently available, but being developed by R&D
(probably IC5042, not sure yet). So you can't do that for now.

Your best bet is to use schCreateWire with the end point of the wire,
to the pin location. Handling rotations isn't a big problem because it's
just a matter of transforming the pin position (find the centre of the pin)
on the master using the transform of the instance.

Regards,

Andrew.

 

As another possible option (albeit not perfect):

I've seen the Cadence tools build a schematic from a Verilog netlist; and
recently, I've seen the tools build a schematic from a CDL netlist (latest
release of DFII on CDBA or OpenAccess).

So, that's another option for you, albeit I understand that autogenerated
schematics don't have the intelligence from the designer, so, your mileage
may vary depending on your needs and deadlines.

So, follow Andew's lead. As Andrew noted, SKILL can do almost anything
(except solve world peace).

Good luck!
SS

 

Simon:
I created a schematic and placed 2 resistors from analogLib and wired
them up. I then exported to a CDL netlist:

*.EQUATION
*.SCALE METER
*.MEGA
..PARAM


..SUBCKT xx
RR0 a b 1K $[RP]
RR1 a b 1K $[RP]
..ENDS


I then tried to import the CDL and generate a schematic from the CDL
netlist. I put analogLib as the reference library and was expecting
it to use analogLib for the resistors but it instead creates a new
cell called res and a schematic view with just 2 terminals.

READING ./netlist

 

Hi Erik,

You need to specify the library containing the primitives as the "schema"
library, not a reference library.

Since for mosfets it expects them to be called "nfet" and "pfet", you'll
probably be better off using "sample" as the schema library and then
substituting them afterwards.

Andrew.