Replace flat vias with symbolic vias

I have a design that was partly drawn with flat rectangular vias.
However, we have since changed via sizes, and the symbolics are now
slightly smaller then before. Now I have a design with a mixture of vias,
flagging thousands of wrong sized vias.

Does anyone have a skill code that will search the hierarchy for flat
vias, calcualte the center point of the via, delete the via, then place a
symbolic via?

 

Hi Master,

I sadly have not got any solution that helps you doing this. I have
written some skill to do a similar job in my past days. Just wanted to
ask you few questions that might help me puting something together:

1. Are your vias single or do you consider arrayed vias ?
2. In case of arrayed vias, is the spacing/enclosure of vias fixed or
array-size dependent as it is very common in advanced process.
3. What if you have a flattened MOS transistor whose D/S diffusions
are very likely to be designed as vias.

In other words, one could end up with a pretty complex script that
might fail some special cases dependently on the complexity of what
you want to manage.
I have learnt over my experience that is very tough to reverse (build-
back) flattened cells.

Regards,
Riad.