Regarding Analog Environment of Cadence + Simulation

Hey all!!

I am working on analog design environment of cadence for my project
work.

To get expertise with the tool I designed a simple amplifier using
npn transistor and simulated it using HSpice simulation tool.

I got errors while simulating due to lack of models for schematic
instances that I used in schematic editor of cadence.

My professor suggested me to go with analog design with the layout
level as start. Is there any feasibility to do like this?(I know it is
a lot of pain) or else am I supposed to follow the schematic editor as
the start?

Need Help

Regards
Chander.

 

Well you probably need to use some sort of design kit, or at the very least
have some models to use with hspice.

Starting from the layout really makes little sense; you end up
needlessly reiterating the layout (which takes quite a lot of work)
when you've not even got the design topology right yet.

Andrew.

 

If you really are a university student, then you should be able to
download a complete Cadence 180nm design, design kit, & documented
step-by-step RF, Analog, Mixed-Signal, Digital, Memory, I/O, etc.
flow (we call it the 'bible') from the Cadence University Web Site
http://crete.cadence.com

This bible (over 1,000 pages) covers every single step, with a
screenshot and discussion, to build a complete SoC, using dozens
of Cadence tools in the custom and digital and physical space.

Very many universities use this design and design kit (which cost
Cadence more than a few million dollars to create) as part of their
normal university curriculum. (Just ask your professors about it).

The Cadence flow engineering team created the chip two years ago
(I presented a paper on it at the Cadence International Users Group).

This chip, code named "Eaglet", takes in a DTMF signal superimposed
on a 2.4Ghz carrier, strips off the carrier, amplifies the resultant
signal 43db, digitizes it to five bits, and then runs a FFT algorithm
partly in ROM, using DMA with the RAMS to store and fetch packets,
outputting an interupt if the correct code (*123) was input in the
first place.

As such, Eaglet contains a wide variety of structures to run Cadence
tools on (sorry, the license does not allow competitors' tools ever):
RF: LNA and mixer
Analog: Op Amp & filter
Mixed-Signal: PLL & ADC
Digital: FFT & DMA
Memory: ROM & RAM
I/O: ESD & Power

Again, this was designed & built at appreciable cost to Cadence,
therefore it is not allowed for commercial use, but, any university
in the Cadence universisty program should be allowed to use it in
their courses & labs.

We are also working on the next-generation designs and design
kits (including hundreds of standard cells) as we speak, so as to
provide our Customers tested platform flows which are proven to go
through all the design steps necessary, and which won't break between
releases.

Ask your professor to contact the Cadence university program to obtain
all you need to design a complete chip - including the design of a
complete chip and a complete design kit!

John Gianni