I am trying to compile and simulate a verilog based design in a Unix environment. I had previously run the same code under Windows and it works there. When I run ncvlog / ncelab / ncsim, it seems to behave as expected (i.e., some typical warnings but no errors). However, when I use signalscan to view the results, it shows that my clock signal is present on the input side of the buffer but not on the output side. I also find that a previous design using the same unisims library behaves in the same manner. It would seem that there is a problem with the primitives in my current library. I've tried to recreate the library with only some success. Can you tell me what steps are required to do this correctly? Thanks in advance. Brian
