Question about First Encounter => Spectre design flow

Hi guys!

This is probably a trivial question, but it has me confounded
nonetheless. I was wondering if anyone could help me.

I've got a design stored as a Verilog netlist. We've also got
technology and standard cell LEF files for First Encounter. These
standard cells are black box cells, meaning that we cannot see the
layout, only the geometry and port locations. We take the Verilog and
LEF files and have First Encounter place and route the design. No
problem there.

Now I want to simulate this placed-and-routed "layout" with Spectre.
What we have: anything First Encounter can export and SPICE models
(implemented as subciruits) for each of the cells. These SPICE models
include parasitics from the original cell layouts). I converted these
models to Spectre format using the SPP command and I changed the
transistor model names to match the transistor models we have.

Now I'm stuck. What's the best way to get a First Encounter layout
(ideally which includes parasitics from the routing) into Spectre so I
can simulate using my standard cell models? I tried using Verilog, but
Spectre doesn't seem to like to simulate Verilog netlists as
'functional' cell views. Do I need to export the First Encounter layout
using DEF files? I couldn't get this to work either. I must be doing
something wrong.

If anyone could help me out I would greatly appreciate it! Thanks in
advance!!!

-Jason D. Bakos

 

I am not familiar with spectre but I doubt you can get it to use a DEF
file. It seems to me that the way to go is to export gate level
verilog from FE which has a straigth forward conversion route to a
spice netlist which you should be able to convert to spectre format.
Also export a GDS from FE (which will be metal only with cell
instantiations) and extract it using an RC extractor (starrcxt etc)
which will give you another spice netlist for the parasitic RCs of the
routes. These two files in addition to the spice of the cell files
should enable you to do a spice/spectre simulation.

 

Hi,

First of all you have to differentiate.
You are talking about a digital design, First Encounter etc.,
in general you do a simulation with parasitics with a
digital simulator e.g. NC-Verilog.
What you get form your place & route tool as parasitic information
is usually DSPF or PDEF format, which has to be translated into
SDF with a delay calculator tool e.g. Pearl or PrimeTime
for your digital simulator.

Spectre is a circuit simulator which needs, you realized this,
spice like transistor models, but also schematics.
If you have the schematics for your standard cells, that's
fine, your are able to simulate.
But that's a different approach, you the try to simulate
a digital design with an analog simulator which in worst
case (big design, lot of transistors) might not be successfully.

What you can do if you need to simulate your digital design in
an analog way you can use a so called Fast spice Simulator
like Cadence UltraSim, Synopsys NanoSim or if it still is
available Nassda's HSim.

Hope this helps a bit,
Bernd

 

Does Cadence have any tools for Verilog=>Spice netlist conversion? I've
used 'spp' before, which converts Spice netlists to Spectre netlists, so
I assume there's something like this for Verilog to Spice (or Verilog
Spectre) netlist conversion.

If not, do you know the names of any other tools that do this?

Thanks!
-Jason

 

yes there are tools to convert verilog to spice. for example, calibre
has a tool called v2lvs to do it. probably it can be done with assura
also. it could also be done quite easily with a script such as perl, and
maybe you can find one somewhere.

also you can import verilog to dfII using Import->Verilog. If you import
a gate-level netlist, you will need to have at least symbols defined for
all the cells that are within your design, and specify the library where
they are as reference library.

if you have symbols for you standard cells, that's fine. otherwise, you
can first import the stubs file from your standard cells library (hope
you have one) to generate a library of symbols for the cells. once this
is done, you can import your verilog with the reference library you just
created and you will end up with a schematic that you can use to produce
a spectre netlist which you can simulate together with the spectre
netlists from your cells.

before being able to netlist properly, you'll need to create stopping
views for your cells, and their CDF, so that they get netlisted as
primitives, otherwise the netlister tries to push into and complains.
I know it sound complicated, but it works and you have to do it once
only. We did this already, so you can email me for more info and some
skill code if you want to do it.

cheers,
stephane

 

also you can import verilog to dfII using Import->Verilog. If you
import

This approach by Stephane sounds reasonable.
Seems to me what you need to simulate are basically:
- transistor-level netlist
- top-level netlist
- simulation test bench
- simulation models

You don't really even need DFII to simulate this, but, I'll assume
you want to use DFII for the sake of this discussion.
It's nice to have a schematic & symbols (although it's not required).

Almost all processes should have a DFII techfile to point to.
This contains primitive symbols and pcells among other things.
If you have the process technology file, point to it in DFII.
If not, create one by reading in the LEF from the digital sc library.
Again, you don't need this to simulate, but it's nice to have.

Then, bring the symbols over from the digital world to DFII
- Most standard-cell libraries contain Cadence CDB symbols
- DFII can read those CDB symbols directly, one for each macro
- If not, most standard-cell libs contain EDIF text symbols
- Read the EDIF 2 0 0 text symbols into DFII
- Again, it's optional to have symbols & schematics; but it's nice.

Bring the sc transistor level netlists over into DFII (if desired)
- Most standard-cell libraries contain CDL netlists for each macro
- Some sc libs even contain the Cadence CDB or OA schematic cell view
- Note: All the Cadence-owned design kits contain sc schematics &
layout
- If the sc lib contains CDB or OA cell views, just point to it in DFII
- If not, read the text CDL netlist to create a CDB schematic
- Note: DFII nowadays creates an editable schematic from CDL.
- The CDB schematic will be ugly, but it will be electrically correct

Now that you have the technology in DFII on CDB or OA, the primitives,
and the symbols - it's time to bring in the top-level netlist into
DFII.

- Read the Verilog gate-level netlist into DFII

Now you should have the entire digital schematic down to the last
transistor (not including parasitics) in DFII on CDB or OA.

Write a test bench and point to the simulation models which came
with the technology file from the library vendor.

I wrote this off the top of my head so you are welcome to dispute
or argue any point.