query in simulation

Discussion in 'Cadence' started by ram, Apr 4, 2007.

  1. ram

    ram Guest

    I designed a first order IIR filter in verilog with floating point
    coefficients.I am writing equivalent C code.What my doubt is is it
    possible to simulate both verilog and C code simultaneously with the
    test vectors defined in verilog test bench.I think there will be
    solution for this case.I am using ncverilog compiler and gcc compiler
     
    ram, Apr 4, 2007
    #1
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