Hello I was performing the pss simulation but some problems occured. Let me describe my system. I'm making PLL which consists: Reference voltage (square wave-vpulse): 4MHz PFD/CP: 3 state, transitor level Loop Filter: second order (R+C) || C VCO (sinusoid): 300 MHz (Verilog-A example from Cadence 'pllLib') Block to change vco sin to square and sent it to Divider. Divider: N=79 (Verilog-A example from "Hidden State in SpectreRF" by Ken Kundert) (I have also transistor level divider and VCO which are working but first I wanted to make pnoise simulation with these two ideal Verilog- A models to save the time) So, the transient simulation shown that PLL locks and the the stabilization time is 10us. Then I set the following parameters of PSS and Pnoise analysyis: PSS: Beat frequency: 4MHz (like desired frequency od out signal of divider) Nr of harmonics: 79 Accuracy Defaults: moderate Additional time for stabilization: 10us (rest of parameters is default. The 'Oscillator' option is not checked) Ok, when I run the pss simulation it was working until 10us. Then I noticed the convNorm was quite big like 27.2e+03 and the analysis was making loops. Nothing more happend so I had too stop the simulation. So there is a problem with convergence. But in transient analysis the ripples of VCO control voltage, after 10us, were like 1mV which means 100kHz variation of VCO frequency (Kvco=100MHz/V). So there shouldn't be any problem. So my question is: Are the pss settings correct? Thanks in advance for replies.