Problems LVS

Hi alltogether,
I tried to do a simple layout (just an inverter-stage).
Everything worked pretty fine, the DRC didn't mention any error, but when
trying to do an LVS the logfile looks like this :

Any idea what's happening ?

Stefan

@(#)$CDS: assura version av3.0:roll-up:dfII4.4.6 03/04/2003 14:46 (source) $
sub-version 3.0.4, integ signature 2003-02-10-1216e

Starting /opt/assura_3.0r01/tools/assura/bin/aveng /home/v0/units/top/
layoutverification/lvs/inverter_lvt_lvs/inverter_lvt_lvs.rsf -exec1 -LVS -cd
slib
/home/v0/units/top/cds.lib
vdbconfig.dat app values:
appNoVariantizeDuplicateCells=1

@(#)$CDS: aveng version av3.0:roll-up:dfII4.4.6 03/04/2003 14:47 (source) $
sub-version 3.0.4, integ signature 2003-02-10-1216e

run on scuis006 from /opt/assura_3.0r01/tools.sun4v/assura/bin/32bit/aveng
on We
d Dec 17 16:35:01 2003

Summary Report: inverter_lvt_lvs.sum
RSF : /home/v0/units/top/layoutverification/lvs/inverter_lv
t_lvs/inverter_lvt_lvs.rsf
Library Name : user_joeres
CDSLIB Path : "/home/v0/units/top/cds.lib"
Cell Name : inverter_lvt
View Name : layout
Rules File : /opt/v1.0.0_pre.8/assura/CC.lvs
Options : -exec1 -LVS -cdslib /home/sdr/sdreu/v0/units/top/cds.lib


Starting dfIIToVdb...
vdbconfig.dat app values:
appNoVariantizeDuplicateCells=1

@(#)$CDS: dfIIToVdb version av3.0:roll-up:dfII4.4.6 03/04/2003 14:50
(source) $
sub-version 3.0.4, integ signature 2003-02-10-1216e


loading /opt/amslayout/v1.1.1/cdb/AMSLayout/.il/
proc/basic.il
AMSLayout SKILL not yet loaded ...
loading contextfiles Ams.cxt, amsLib.cxt, amsUtil.cxt, amsModulgen.cxt,
amsFront
end.cxt
*************************************************************
* Ams - Generic Module Generator Library and DFII Addons *
*************************************************************
start Ams package initialization ...
Searching & Linking Repositories ...
done

***loading technology specific pcells:
blockCaps.il cap_sandwich.il extendSymbols.il inverters.il
mimCap.il

***loading project specific pcells:
no project specific pcell found

ifxamsinitializeTechnology()
loading techfile: /opt/amslayout/v1.1.1/skill/if
xams_init_technology.il
initializing rules table for ruleset "default"
initialize AMSLayout Rule-Set for CC (revision 1.4.8)
scanning precompiled rules from "/opt/amslayout/
v1.1.1/skill/ifxamsCompiledRules_default.il" ...
loading precompiled rules from
"/opt//amslayout/v1.1.1/skill/ifxamsCompiledRules_default.il" ...
successfully initialized rules table
initializing pcells
initialize p-cells
ifxdevlayout: Trying to load skill code...
adding siminfo for "ptranspair_crossed"
adding siminfo for "ntrans"
adding siminfo for "ptrans"
Loading netlist addons for ifxdevsymbol ...
.... done.
*WARNING* could not find the standard addon library*WARNING* could not find
the
standard addon librarysuccessfully initialized pcells
Amslayout package succesfully initialized.
*WARNING* could not find the standard addon library
Checking layers...
Compiling rules...

warn: Undefined purpose in dfII.
Purpose name 'qmg' doesn't exist, ignoring this purpose.
capqmg = layer("Capacitor" type("qmg"))

WARNING! There is no switch for last metal in the
control file.
error: Layer 'po1' must be connected.
2309. po1_3065_terminal = _geomPushDown(po1 pgates)
error: Layer 'psd' must be connected.
2310. psd_3066_terminal = _geomPushDown(psd pgates)
error: Layer 'nwell' must be connected.
2311. extractMOS("phvt" pgates (po1_3065_terminal "g") (psd_3066_terminal
"s"
"d") (nwell "b") (cellView "c_bptrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2320. po1_3083_terminal = _geomPushDown(po1 pgates_sram)
error: Layer 'psd' must be connected.
2321. psd_3084_terminal = _geomPushDown(psd pgates_sram)
error: Layer 'nwell' must be connected.
2322. extractMOS("phvtsram" pgates_sram (po1_3083_terminal "g")
(psd_3084_term
inal "s" "d") (nwell "b") (cellView "c_bptrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2331. po1_3101_terminal = _geomPushDown(po1 phgates)
error: Layer 'psd' must be connected.
2332. psd_3102_terminal = _geomPushDown(psd phgates)
error: Layer 'nwell' must be connected.
2333. extractMOS("phvtbl" phgates (po1_3101_terminal "g")
(psd_3102_terminal "
s" "d") (nwell "b") (cellView "c_bptrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2342. po1_3119_terminal = _geomPushDown(po1 ngates)
error: Layer 'nsd' must be connected.
2343. nsd_3120_terminal = _geomPushDown(nsd ngates)
error: Layer 'bulk' must be connected.
2344. extractMOS("nhvt" ngates (po1_3119_terminal "g") (nsd_3120_terminal
"s"
"d") (bulk "b") (cellView "c_bntrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2353. po1_3138_terminal = _geomPushDown(po1 ngates_acc)
error: Layer 'nsd' must be connected.
2354. nsd_3139_terminal = _geomPushDown(nsd ngates_acc)
error: Layer 'bulk' must be connected.
2355. extractMOS("nhvtaccsram" ngates_acc (po1_3138_terminal "g")
(nsd_3139_te
rminal "s" "d") (bulk "b") (cellView "c_bntrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2364. po1_3156_terminal = _geomPushDown(po1 ngates_pld)
error: Layer 'nsd' must be connected.
2365. nsd_3157_terminal = _geomPushDown(nsd ngates_pld)
error: Layer 'bulk' must be connected.
2366. extractMOS("nhvtpldsram" ngates_pld (po1_3156_terminal "g")
(nsd_3157_te
rminal "s" "d") (bulk "b") (cellView "c_bntrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2375. po1_3174_terminal = _geomPushDown(po1 bhgates)
error: Layer 'nsd' must be connected.
2376. nsd_3175_terminal = _geomPushDown(nsd bhgates)error: Layer 'bulk'
must be connected.
2377. extractMOS("nhvtbl" bhgates (po1_3174_terminal "g")
(nsd_3175_terminal "
s" "d") (bulk "b") (cellView "c_bntrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2388. po1_3194_terminal = _geomPushDown(po1 plgates)
error: Layer 'psd' must be connected.
2389. psd_3195_terminal = _geomPushDown(psd plgates)
error: Layer 'nwell' must be connected.
2390. extractMOS("preg" plgates (po1_3194_terminal "g") (psd_3195_terminal
"s"
"d") (nwell "b") (cellView "c_bptrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2399. po1_3212_terminal = _geomPushDown(po1 plgates_sram)
error: Layer 'psd' must be connected.
2400. psd_3213_terminal = _geomPushDown(psd plgates_sram)
error: Layer 'nwell' must be connected.
2401. extractMOS("pregvtsram" plgates_sram (po1_3212_terminal "g")
(psd_3213_t
erminal "s" "d") (nwell "b") (cellView "c_bptrans ivpcell ifxdevsymbol"))
error: Layer 'po1' must be connected.
2410. po1_3230_terminal = _geomPushDown(po1 prgates)
error: Layer 'psd' must be connected.
2411. psd_3231_terminal = _geomPushDown(psd prgates)
error: Layer 'nwell' must be connected.

[...]

Errors exist in the rules file '/opt/v1.0.0_pre.8/assura/CC.lvs'.


***** dfIIToVdb terminated abnormally *****

*WARNING* Translation abnormally terminated!

*WARNING* /opt/assura_3.0r01/tools/assura/bin/aveng exit with bad status
*WARNING* Status 256
*WARNING* Assura execution terminated


***** aveng fork terminated abnormally *****

 

I assume you are designing with an Infineon design kit.

In the Assura LVS GUI there is a field called 'Switch Names',
you have to set a switch with 'Set Switches'.
For your design kit you have to choose your process metal
options as switch.

Hope I explained it clear enough, but this is only an assumption.

Bernd