problem with veriloga model

I made a veriloga file and related symbol. I think I have already
combine them together.
It works before, but doesn't work this time. I am not sure what is the
reason for this.

It says:

ERROR (OSSHNL-116): Unable to descend into any of the views defined in
the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'I0' in cell 'diodepara'. Either add one of these views to
the library 'research',
cell 'diodemodel' or modify the view list to contain an existing view.

End netlisting Sep 25 14:58:32 2008
ERROR (OSSHNL): Error(s) found during netlisting. The netlist may be
corrupt
or may not be produced at all.
To generate correct netlist, fix the errors and re-netlist.
...unsuccessful.

Thank you very much!

 

Hi There,

Have you got a view called 'veriloga' for cell research/diodemodel ?
The 'veriloga' view is part of your switch viewList but does not seem
to be found for that particular cell.
BTW, which simulator are you using ? Spectre from ADE or any other
config using the HED ?
The more information you provide the best to get it solved.

Cheers,
Riad

 

Hello Riad,

Thank you so much for your reply. I use Spectre from ADE.
What is "view"? you mean "cellview"? Yes, I think so.I made a file
which is in veriloga format.
I tried to make a schematic and symbol out of it, so I can put it in
the library to use.
I don't know whether I have some wrong steps to follow, maybe.
Do you know any help file or examples to follow?

Thank you so much!

 

Hello Baobao,

I honestly don't understand what do you mean by 'I tried to make a
schematic and symbol out of it' :-(
I would advice the following flow as an example:
1. Create a new verilog-A cellView from your Lib Manager -> New ->
View and fill up the poped form. This is a little exmpample:
http://riad-kaced-usenet-group.googlegroups.com/web/pic01.png?gsc=RHfB_AsAAAChh_UigiaDfLU9K0ICidPT

2. Step1 should come with a text editor including a verilog-A template
you need to complete. There is the code for my example:

// VerilogA for rkWorkLib, rkSampleHold, veriloga
// The core is from the designers-guide.org's Guide (www.designers-
guide.org).

`include "constants.vams"
`include "disciplines.vams"

module rkSampleHold(Pout, Nout, Pin, Nin);

input Pin, Nin; voltage Pin, Nin; // input port
output Pout, Nout; voltage Pout, Nout; // output port
parameter real period=1 from (0:inf); // sampling period (s)
parameter real toff=0 from [0:inf); // offset time for sampling (s)
parameter real td=0 from [0:inf); // delay from sampling to output (s)
parameter real tt=period/100 from (0:inf); // duration of output
transitions (s)
integer n;
real tstop, save;

analog begin
// Determine the sample time
n = ($abstime - toff) / period;
tstop = n*period + toff;

// Sample the input
@(timer(tstop) or initial_step)
save = V(Pin,Nin);

// Produce output with well-controlled transitions
V(Pout,Nout) <+ transition(save, td, tt);

end

endmodule
//

When you save and close the file editor, your code will be checked and
compiled. When everything's alright and the symbol does nt exist, the
Create Symbol form pops out to create a new symbol. It is pre filled
with the pins as defined in yoyr verilog-A file.

So if you manage to come at the end of this, then your cellView ends
up with 2 views: veriloga and symbol.
Create another schematic for the testbench, instantiate the symbol you
have recently created and simulate. Simple as that ! When you descend
the sybol, it will go to the verilog-A code. I suppose yoy haven't got
any other views rather than symbol and veiloga.

That's it, hope it is better now

Best Regards,
Riad.