Problem with gated clocks in RTL compiler

Discussion in 'Cadence' started by wantcar, Jun 30, 2007.

  1. wantcar

    wantcar Guest

    After inserting clocking gating, I got a bunch of errors like:

    the following sequential clock pins have no clock waveform driving
    them, no timing constraints will be derived for paths leading to or
    from these pins

    I traced back the pins and they are all connected to ouputs of clock
    gating device added by RTL compiler itself. Specifying each gated
    output clock (create generate clock with freq divide 1?) doesn't seem
    to be a logic answer since this would have to be done for EACH output
    of clock gating device.

    Thus I am wondering if there's some attribute I missed in RTL compiler
    that can deal with this easily. Thanks!

    -Jerry
     
    wantcar, Jun 30, 2007
    #1
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