I have a large analog chip and I am trying to write a checker for functional verification and I need to be able to see signals in various parts of the hierarchy. In veriloga, how do I get the value of I1/I2/I3/V(some_node)? I figure I need currents and variables as well. For voltages, I thought about adding pins to blocks and propogating the signals that way, but there are too many of them and it doesn't help with the currents or variables... I haven't found any reference to doing this in the documentation either... did I miss it? David Reynolds