Power Striping strategies in BG and SE

Hi...
I am trying to place and route a 128 bit multipler, with 4 pipelined
stages. I am using the datapath option of PKS and their AWARE
components to get the gate level netlist.
I import this netlist into SE and follow the usual methodology from
there on, i.e. FLOORPLAN, PLANPOWER, PLACE AND ROUTE.
HOwever, When i add stripes in plan power and then check for geometry
violations, I get antenna violations towards the edges of the stripes,
where they meet the core boundary. I am not sure if this will affect
the WROUTER when it tries to route the design. However, it seems like
the wrouter finishes with 10-15 violations remaining. What are the
usual strategies if violations are remaining after wrouter finishes
its first run.

Any help will be greatly appreciated, thank you
Student