Power calculation using SoC Encounter

Discussion in 'Cadence' started by ajay.j.joshi, Sep 9, 2008.

  1. ajay.j.joshi

    ajay.j.joshi Guest

    Hi,

    I synthesized my verilog code for multiplier using Cadence RTL
    Compiler and placed/routed the design using SoC Encounter. I want to
    calculate the power dissipation of my design using SoC Encounter. I
    know one can use the following set of commands.

    setExtractRCMode -detail -noReduce
    extractRC
    updatePower -noRailAnalysis -report power1.rpt -mode layout -clockRate
    1000 -toggleProb 0.2 -biasVoltage 1 VDD

    However, here the toggle rate the fixed at 0.2 for all components. I
    want to use the activity stored in the .vcd file generated by running
    the verilog netlist generated by Encounter as it would give a more
    realistic estimate. How do I do that?

    Thanks in advance

    Regards,
    Ajay
     
    ajay.j.joshi, Sep 9, 2008
    #1
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