Port order Mismatch in spectre netlist

Hi,
I am using spectre version 7.20.202.

I have a design with multiple hierarchy, if I make any change in the
some schematic deep down the hierarchy (specially related to ports) I
start seeing issues of port order or sub-circuit not matching with the
call instance in the parent cell. This problem goes away if I do a
check and save of the parent cell (without making any change in parent
cell).

Problem is that once this issue appears it is very hard to root cause
(specially if design has lot of hierarchical cells)

Is there any way to avoid this issue, or any way to switch from "map
by order" to "map by name".

Regards,
Atul

 

Atul Agrawal wrote, on 09/15/10 08:32:

Atul,

This should not happen, so I would suggest you contact Cadence Customer Support.
Note that it's the IC version that matters here, not the spectre version.

Mapping by name is not supported in spectre.

Regards,

Andrew.