plotting internal verilog-A signals

Discussion in 'Cadence' started by danmc, May 7, 2006.

  1. danmc

    danmc Guest

    I have a verilog-A model with

    electrical foo;

    but foo does not connect directly to a pin on the module. Is there a
    way to plot v("foo")? I tried looking in the results browser in analog
    artist but didn't see it.

    Thanks
    -Dan
     
    danmc, May 7, 2006
    #1
  2. danmc

    Andrew Beckett Guest

    You'd either need to save all voltages, or use the nestlvl option to
    control hierarchy levels to ensure that voltages within the module
    are saved.

    Regards,

    Andrew.
    Andrew Beckett
    Principal European Technology Leader
    Cadence Design Systems, UK.
     
    Andrew Beckett, May 9, 2006
    #2
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