pks help in adding power stripes

Discussion in 'Cadence' started by eda_cadence, May 5, 2005.

  1. eda_cadence

    eda_cadence Guest

    hi friends
    i set floorplan for my design as follow
    cluster (chip )size
    Top - bottom (0 -58)
    left - right (0-57)
    i/o - core
    spacing for all t,b,l,r is 4

    how i set power stripes for metal layer in Umc18 lef library
    for met6 spacing is 0.60 and width is 0.44(i read from lef library).
    please help what data i have to set in
    stripe width =?
    number of stripes =?
    net names =?
    start from distance =?
    stop from distance =?
    stripe spacing =?
    net spacing =?

    and i also wanna know in what way i can set the number of power
    stripes.
    thanks
    regards
    aravind
     
    eda_cadence, May 5, 2005
    #1
  2. eda_cadence

    mk Guest

    set_power_stripe_spec documentation is pretty clear but I hope I can
    help you with some suggestions. The number of stripes and the width of
    stripes are determined by how much power your block requires. A rough
    rule of thumb is to use 1 micron per mA of power you need. To decide
    the power you can use an estimate based on how many nand2 equivalent
    cells you have, what frequency you're running at etc. The standard
    cell library docs should have some method of estimating power
    consumption of individual cells.
    The net names should be the same as that you get from the cell
    libraries LEF file. Use the same net names which appear in the macro
    lef. Each cell should have a power and ground pin (usually VDD and
    VSS).
     
    mk, May 5, 2005
    #2
  3. eda_cadence

    eda_cadence Guest

    thanks mk,
    but i didnt get your point, 1u/mA means, ur telling about width of
    power stripes or number of power stripes, pls tell with an example then
    only i can understand. i m not so brillant to understand immediately.

    is it any way/command to find number of nand equalivence in my design.
    pls explain with an examples
    thanks
     
    eda_cadence, May 5, 2005
    #3
  4. eda_cadence

    mk Guest

    The product of the two. In other words, estimate the total power
    requirement and bring in enough metal to carry the current. This tells
    you the total width of all stripes. You also have to consider that the
    row VDD,VSS connections have some IR drop so you have to distribute
    this total metal more or less evenly across the macro so put one
    VDD,VSS stripe per 150~200U. So if you need 100 mA, use total of 100U
    of VDD and VSS and distribute it into 20~30U stripes of say 5 micron
    apart.
    "report_area -hi -cells" in PKS. Find the area of nand2(x1) and
    divide the total size to that number.

    hope this helps.
     
    mk, May 5, 2005
    #4
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