PKS 5.0/Ambit (Verilog) global define?

Discussion in 'Cadence' started by hmmmm, Jun 20, 2004.

  1. hmmmm

    hmmmm Guest

    In Synosys's Design Compiler family, the Verilog-macro `DC is
    always defined. It's analogous to commercial C-compilers --
    MS's Visual-Studio does a "#define MICROSOFT_C" before scanning
    any source-files. This can be useful, for writing code that needs
    specific workarounds for specific tools.

    For example, here's how I use the `DC in my simulation models.

    ....

    `ifdef DC

    // If Design-Compiler, *FORCE* a deliberate syntax!
    IM_SORRY_DAVE_IM_AFRAID_I_CANT_DO_THAT

    `endif

    ....

    Very trivial, but if someone attempts to run my code through
    Design-Compiler, it auto-fails. This is a useful safeguard
    for small-RAM models (which may be synthesizable in Xilinx or
    other FPGA-tools)

    Does PKS 5.0's Verilog-reader have a similar feature? I've waded
    through three to four cdsdoc PDFs (on coding-style, Verilog Datapath
    extension, etc.), but I can't find the information I want.
     
    hmmmm, Jun 20, 2004
    #1
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