Pipeline ADC Digital Correction Algorithm

Discussion in 'Cadence' started by Vincent, Jul 10, 2004.

  1. Vincent

    Vincent Guest

    Dear all:



    I'm designing a 12bit piepline adc (very conventional one). it's based
    on 1.5bit/stage + 3bit (last stage). In some papers and products
    specs, there are more than enough stages over all, say: 12 1.5bit
    stages and one 3bit stages. I'm just wondering what algorithm in this
    case, after RSD digital correction, there will be 15bit resolution and
    discard last 3 stages?! What's benefit behind this "luxurious"
    correction?

    Appreciate your help.



    Vincent
     
    Vincent, Jul 10, 2004
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. Creating a Surface (Digital Terrain Model) from random 3D points

  2. Help to correction my code

  3. Mixed signal spectreSVerilog can not display digital waveform

  4. *Error*outputs: digital terminal outputs not supported

  5. disable saving of digital signals

  6. ADC Control Logic - Simulation

  7. Gamma correction for Photoworks 2006

Loading...