Physically Hierarchical design flow in PKS and SE

Hello dear all.

I am having a number of questions in performing a physically
hierarchical desgn in PKS and SE. I would appreciate any help that
would make this flow more clear to me:

I am doing hierarchical placement of a design in PKS(V5.13) using
'clusters'
and with a script like this:


------------------------------------------------------------------
importing libs, importing the design ......
..
..
set_current_module top_level
create_physical_cluster -name Cluster1 inst_1 -allow_place_overlap
false- -allow_route_overlap true -type
soft_block
do_push -instance inst_1
set_floorplan_parameters -bbox_initial {0.000 0.000 41.580 43.120}
create_physical_instance phys_inst_1 -macro macro_of_inst_1
-location {0 0}
do_pull Clester1
..
..
- optimization (stop before final route)
- saving top level design in Verilog and DEF format
------------------------------------------------------------------


Where macro_of_inst_1 macro is P&Red in advance and imported to PKS
in LEF format.

Then I need to import the outputs of PKS to Silicon Ensemble(v5.30) to
perform
final wroute, RC extraction and timing analysis (because of licemse
problems).

Now my questions are:

0- does the PKS script above seem correct?

1- which files exactly do I need to import to SE in order to keep all
the physical information plus the hierarchy??

2- Should I import both verilog and DEF formats? Does SE automatically
match the corresponding logical and physical blocks together?

3- how about PDEF format? is it the format that should be used instead
of DEF for hierarchical designs?

4- After the design is routed, in order to perform static timing
analysis, I tried to import tlf models of my lower level blocks from
PKS to SE along with the standard tlf libraries, but SE complains
about 'syntax error in name_space' when reading in the TLF files that
I have generated in PKS. Is it a problem of version uncompatiblity
between pks and SE or is it a more
serious problem? does anybody have any solution for it?

I would very much appreciate any sort of helping in any of the above
questions or pointing to good tutorial for hierarchical physical
design in PKS or SE.

Thanx in advance,
- Max Edmand

 

Don't get your hopes up. A few of my colleagues told me
Cadence is pushing "SOC Encounter" as their hierarchy/floorplan/
synthesis tool. At one time, Cadence may have 'mentioned'
physical hierarchy support using SE-PKS, but my same colleagues
told me there were a bunch of 'provisos/caveats/bugs/etc.'

In other words, Cadence doesn't officially support that type
of usage (even if its possible with some manual workarounds.)