PCELL problem (distorted flattened cells)

Hi,

I am having a problem with pcells. When I flatten (either directly or
through export) some cells distort. Specifically it seems to be
affecting large nmos and pmos devices. I am using tsmc 0.25 process
with files that I obtained through the MOSIS foundry so everything
should be fine. This is a MAJOR problem as I cannot submit my design
until I get this worked out.

Anyone had this problem or have any suggestions??

Regards,
Michael

 

Problem Solved,
Cadence version compatibility issue.

Michael

 

The problem I had was that I was using cadence 4.4.6 with files that
required 5.0+. This caused the PCELL to be misinterpreted under
certain conditions (like flattening). I did just need to stream out,
but I needed to convert the PCELLs to geometry, which was giving me the
same problems a when I flattened them. The part that was confusing me
was that the PCELL was correct when I used "shift-f" but was definetley
not correct when I flattened. This was solved by upgrading to the
needed version of ic.

Let me know if there are any more questions?

Regards,
Michael