Parasitic capacitance values for hand calculations?

Hi all!

Despite having reviewing some previous posts about the values reported
by Virtuoso for the small-signal parasitic capacitances of transistors
(e.g. see http://groups.google.com/group/comp...read/thread/4fbe2dbd2ed1afa1/e0f324447dc2887f
or Sourcelink Solution Number 1814346), I am still unable to figure
out how to convert these values to others useful for hand
calculations.

For instance, the Sourcelink solution states-among many other
equations-that:

....
cgd = Cgd - Cgdovl
Cgdovl = pInst->pSDModel->OverlapCgd * pInst->MFactor;
....

On the other hand, for a particular simulation I am getting
cgd=-226.9a and cgdovl=166.3a. According to the above equation, then
Cgd = cgd+Cgdovl=-60.6a. So I wonder...

Is this the correct way for obtaining the values of the "physical"
parasitic capacitances of a transistor (Cgd, Cgs, Cdb, Csb, Cgb,
etc.)?

-If no, then... how can they be properly calculated from the values
reported by Cadence?
-If yes, ...how should I interpret, for instance, the result
Cgd=-60.6a (negative)? From the formal definition, I guess this means
that the gate charge decreases as the the drain voltage increases...
BUT what capacitance value should be actually drawn in a pencil-and-
paper schematic between the gate and the drain?

Thanks in advance for your help!

Regards,

Jorge.

 

Hi Jorge,

The last time I was doing propoer IC design work was 5 years back.
At that time, I was rather using the very basic equations you can find
in any descent analog book.
For example, the equation to compute the Drain-bulk capacitance is
given by:

Cdb={(AD*CJ)/(1+Vdb/PB)^MJ)}+{(PD*CJsw)/(1+Vdb/PB)^MJsw)}
Cdb= Area contribution + SideWall contribution.

1. AD and PD are the Area/Perimeter of the drain junction
2. Vdb is the Drain-Bulk voltage
3. CJ, MJ, CJsw, MJsw, PB are process parameters you can get either
from your model card or from any document that is provided by your
foundry:
-> CJ=Zero-bias junction bottom capacitance density.
-> MJ=Bulk junction bottom grading coefficient.
-> CJsw=Zero-bias junction sidewall capacitance density.
-> MJsw=Bulk junction sidewall grading coefficient.
-> PB=Bulk junction built-in potential

You can calculate the Csb the same way.
Give a look at the gate capacitance in any of your books as well.

I'm always taking the very simple equations when it comes to make a
first hand made design. I then play around with the simulation to
tweak the values of each single transistor.

Hope this helps.

 

Hi Riad, thanks for your kind reply!

As a matter of fact, my interest in obtaining these capacitances
directly from the simulator is that I want to compare those values
with the ones I get from my hand calculations, using the theoretical
expressions. Indeed I was using the theoretical expressions for
estimating the parasitic capacitances, but the results I get seem to
be very different from the ones calculated by the simulator, because
the predicted behavior of the circuit is not too much in agreement
with the simulated response. Thus it would be really helpful if I
could see what are the parasitic capacitances calculated by Spectre
and compare them with my theoretical calculations to see were my
mistakes are...

Furthermore, I am a little confused about how to correctly apply some
of the expressions found in books. For instance, Allen's book says the
gate-source overlap capacitance is

Cgs(overlap) = Cox*Ld*Weff

where Cox is the oxide capacitance, Ld is the overlap between gate and
source, and Weff is the effective channel width. When I try to use
this expression, I find the following issues...

1. Cox is not found in the (BSIM3v3) model file. I only have dox
(oxide thickness), which along with the SiO2 permitivity I use to
calculate Cox=eox/dox. The parameter Ld is also not found in the model
file. I only have the Lint parameter, and since the BSIM manual says
Leff=Ldrawn-2Ld, I suspect they are equivalent. However, in my model
file this parameter... is negative!!!!! I was told (see
groups.google.com/group/comp.cad.cadence/browse_thread/thread/
35bbed8ae25e846a/a7ed4316a8f3c027) that this is due to model fitting,
but unfortunately this doesn't resolve the problem of how to calculate
Cgs(overlap) using the theoretical expression.

2. The book also says, if you have spice models you can forget about
the previous expression and just use Cgs(overlap) = CGDS0*Weff. Now
CGDS0 does appear in the model file, but then I get different values
when using the two expressions! What value is "more correct"? I would
like to know by "seeing" what is Spectre calculating...

To summarize, I think having the possibility to see what are the
parasitic capacitance used by the simulator is the only way in which I
could spot my hand-calculation mistakes and, most importantly, get the
required insight about what approximations should/can be done when
estimating the values of those parasitic elements.

It would be really interesting to hear how other designers estimate
the parasitic elements when performing their hand calculations.
Unfortunately I am currently in the academia and not in the industry,
and there are no practical designers around here at the moment

....Any further advice about this issue is welcome. Thanks again for
any help!

Cheers,
Jorge.

 

Dear Jorge,

I would like to remind you that for modern processes due to LDD
structures CGD capacitances are voltage dependent, since depletion
region capacitance in Lightly Doped areas is voltage dependent.

Cheers,
Ozgur

 

I would like to remind you that for modern processes due to LDD

Really? ...this is getting worse than I thought! :S
Could you recommend any book or paper where I could learn more about
how to take into account this at design phase?
Thanks for the info!

Regards,
Jorge

 

Jorge,

You might find this thread worthy of a look :

http://groups.google.com/group/comp.cad.cadence/tree/browse_frm/thread/4fbe2dbd2ed1afa1

If you take a look at BSIM4 manual for instance, you will see that it's almost 200 pages in length,
most of it filled with equations. Now you're basically asking how to reduce these 200 pages to a
single equation, unfortunately it's not possible. And due to the complexity of the model, there's no
one-to-one correspondence between BSIM parameters and simple hand-calculation model.

If you really want those numbers, the simplest way is extract the model yourself by matching it to
simulation results. You should be aware that a simple model will be valid only for specific
transistor geometries, bias and operating conditions.


Good Luck,
Stéphane

 

You can take a look at capacitance modelling section in BSIM3 Ref.
Manual Chapter 4 at UC Berkeley BSIM official site.

http://www-device.eecs.berkeley.edu/~bsim3/get.html

Ozgur

 

Dear Jorge

I do concur with Stéphane. It is too ambitious trying simulator
parameters for hand calculation. a spectre -h command shows that
BSIM3V3 makes use of 358 model parameters against 864 for BSIM4.
besides, unlike surface potential models, BSIM is less physical based
and full of curve fitting equations. It's not the best model suitable
for hand made calculations.

As other chaps mentioned earlier, the MOS G/D/S capacitance are
dependent of the voltage at the given node. For more details, Please
give a look at the following slides:
http://bwrc.eecs.berkeley.edu/IcBook/Slides/chapter3.ppt

As explained in the SR you've mentioned above, The gate capacitance
computed by BSIM are not physical. Cgs and Cgd are not two-terminal
capacitance. Drain voltage has actually an effect on Cgs, even though
the drain is not directly connected to that "capacitor". That's the
way BSIM works and it has nothing to do with Spectre. BSIM computes
the MOS capacitance using a charge-based approach and this needs the
charge equations for all four terminals.

Another difficulty to compute the D/S capacitances based on the Qd/
Qs charges is the fact that only the total channel charge QINV =QD +QS
is really known. BSIM uses a partition factor (XPART) to compute both
Qd/Qs. BSIM has 3 partition schemes: 0/100, 50/50 and 40/60. Only the
latter is physical-based. Please refer to the BSIM manual for more
information aboy this.

My advice is to keep your equations very simple for hand calculation.
BSIM will rather give you some head-eachs ;-)

 

Thanks everybody for your kind replies and suggestions! I realize now
that it's impossible to (directly) conciliate the hand calculations
with the BSIM parameters...

After skimming through the literature, I have the feeling that the
topic of PRACTICAL hand-calculation of parasitic capacitances is
rather understimated in most analog IC design books. I guess a thread
"What are your favorite expressions for estimating parasitic
capacitances for design purposes?" in this forum would be a sure
hit!

....Anybody willing to share this kind of practical knowledge?

Cheers,

Jorge.