Parallel simulation consistency?

Discussion in 'Cadence' started by Gary Thorpe, Jul 20, 2005.

  1. Gary Thorpe

    Gary Thorpe Guest

    Hi,

    I am using ncvhdl, ncelab, and ncsim to perform some VHDL simulations. I
    would like to know if doing the following would cause problems with the
    simulations:
    I.e. can I elaborate the design, start simulating that, re-elaborate it with
    different parameters, and start another simulation in parallel? Will this
    cause any problems or inconsistencies?
     
    Gary Thorpe, Jul 20, 2005
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. parallel view control

  2. Finding parallel features

  3. parallel lines into a single line

  4. parallel process

  5. advance simulation time without running simulation and then re running

  6. Ya gotta luv the consistency!?

  7. titleblock consistency

Loading...