OP-Amp design question

Hi,
we are designing a SiGe OTA. However, we met several problems
that we can't solve by ourselves:

1. When we plot the Bode frequency response for a simple common emitter
SiGe amplifier with either resistor or active load, we found a
zero-pole pair well before the first dominant pole. This produces a
increase in dc gain for mid frequencies since the zero occurs before the
pole. While the origin of the dominant pole is along expected lines we are
unable to understand why this zero-pole doublet shows up.


2. We are interested in measuring the dc gain (greater than 90db) and fT
(greater than 1G), settling time and phase margin on the fabricated chip.
Is there any reference on the test circuits we must include on chip so
that these measurements can be made?



sincerely

 

do you use the cascode gain-boosting configuration ?
this is known to produce doublets in transfer
function.
have a look at
- http://www.elec.ucl.ac.be/enseignement/ELEC2650/chapter5.pdf
- http://www.imec.be/esscirc/papers-96/25.pdf
if it is the case. else, you should maybe provide more
details about your opamp.

hope this helps,

stephane