nport and layout LVS

Hello,

My schematic has many n2port components that I'm using to import
s-param for different things. My question is how can I avoid LVS errors
while generating my layout through XL editor (pcells)? As it currently
stands the layout won't match the schematic because of those n2port
components. This is a specific case but in general how can you tell
LVS to ignore part of the schematic, etc? Hopefully someone knows what
to do here. Thanks

-Mike

 

Mike:
Add a property called lvsIgnore to the n2port in the schematic. Note
its type is boolean and set it to t. I don't know why this isn't
already set for the components in analogLib.

 

Hi Erik,

Thanks for the reply. I'm basically ADS guy and don't know too much
about Cadence. What do you mean by 'adding a property called
lvsIgnore'? How do I add a property manually for a component? Also,
exactly what's this lvsIgnore doing? Meaning, I have a node(1) that
connects to n2port and the output/other side node(2) connects to a
resistor; would LVS still know that the node(1) wire through something
(n2port thing) should connect to the resistor? I don't know if the
question is making any sense. At least please let me know how to add
that lvsIgnore property. Thanks

-Mike

 

Hi,

Sorry I asked the question before looking into it. I found out how to
add property but after I set the type to boolean it didn't provide a
textbox to enter value 't'. Any suggestions??

-Mike

 

If you make it boolean, you can just turn on the checkbox that is shown. That is
setting the value t but in a more graphical way...

Andrew.

 

Mike:
By adding the lvsIgnore property this instance will be ignored totally
and won't show up in the schematic netlist used for LVS. If you still
want LVS to netlist the connectivity I would recommend creating a
schematic_lvs view for the n2port and connect your ports with metal
resistors or cds_alias components.