New book: SystemVerilog Assertions Handbook

I am pleased to announce the release of our new book
SystemVerilog Assertions Handbook which addresses SVA Assertion-Based
Verification language along with pragmatic applications and guidelines
in the use of SystemVerilog Assertions.

For more information on the book, please read the preface / backcover
at
http://www.abv-sva.org/

Ben Cohen
_________________
Ben Cohen Trainer, Consultant, Publisher (310) 721-4830
http://www.vhdlcohen.com/
* Co-Author: Now available: "SystemVerilog Assertions Handbook", ISBN
0-9705394-7-9
* Co-Author: Using PSL/SUGAR for Formal and Dynamic Verification 2nd
Edition
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115