Netlist Reduction Tool Jivaro

Discussion in 'Cadence' started by Frank Nitsche, Jun 1, 2006.

  1. Frank Nitsche

    Frank Nitsche Guest

    Hi everybody,

    yesterday I've heard from a tool named JIVARO. Does somebody has any
    experiences with this tool. It shall reduce parasitic netlists (e.g.
    from DRACULA or ASSURA) to reduce the simulation time of the post
    layout simulation.

    Best regards, Frank.
     
    Frank Nitsche, Jun 1, 2006
    #1
  2. Frank Nitsche

    Bernd Fischer Guest

    Frank please contact me directly bernd <dot> fischer <at> xignal <dot> com

    What exactly do you want to know?

    Bernd
     
    Bernd Fischer, Jun 1, 2006
    #2
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. Can I do LVS between gate netlist and transistor netlist in Diva?Thanks

  2. ocean design() function wants netlist to be named netlist

  3. Is there any tool to convert netlist to schematic?

  4. A free graphical netlist trace and modification tool

  5. Netlist Reduction

  6. Free netlist ECO tool

Loading...