Net names in Allegro

Hi,

I have a difficult variation on a very simple subject.

In my design, I have the situation where (for reasons logical at the
time), one net with a unique name, goes into a bus with another unique
name, which then goes into a bus with another unique name. This occurs
through out the design and we have been able to verify (from the
netlist) that the tools have been able to resolve this routing (logic
routing that is) without error.

The problem that I have is that the mapping in the tools, when viewed
globally, is somewhat arbitrary. Whereas one net will have the first
net name, some will have the net name of the second bus, and some may
have the mapping of the third bus. There is no common naming scheme
applied by the tool when resolving the netlist.

Example below:

A (component) -> a1_net -> b2_bus<5> -> c3_bus<12> -> B (component)

The name that the tools see can be either:

a1_net, b2_bus<5> or c3_bus<12>

Even though they are all the same logical net.

Is there some way to specify in the design the global net name
throughout the design (as a mapping between component A and component
B), instead of -say- some arbitrary combination of multiple nets? So,
in the above example, is it possible to have the tool always recognise
the net as a1_net, and not any of the others?

Kind regards,

Stephen