Negative wireload model

Discussion in 'Cadence' started by Arturi, Nov 8, 2003.

  1. Arturi

    Arturi Guest

    Hello there!
    I'm synthesizing a design with cadence BuildGates. Since the wireload
    models of my libraries are very unrealistic I'm over constraining the
    design and setting the wireload to 0K type mode top (i.e. no wireload
    at all). My problem is that the synthesis tool sees in some nets
    negative wireloads. What does that mean?
    If I set the same constraints to the generated netlist in order to do
    a STA check these same nets have 0 wireload and therefore I get
    negative slacks.
    What can be causing the tool to see negative wireloads?? And what do
    they mean??
    Thanks in advance.
     
    Arturi, Nov 8, 2003
    #1
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