NC-Verilog netlisting

Hi,

Here's my situation: my design group recently migrated over to IC
Manage for revision control. I've been happy, except for this one
'gotcha' that I've found. My design is a large analog design that is
made up of ECL gates and a some other analog circuits. I've modeled
everything at the gate level using verilog. To netlist and simulate
the functionality of this very large block, I would pull up NC-Verilog
and ask it to create a netlist, starting at the top-level of the
hierarchy. It would traverse the hierarchy, and wherever it found a
verilog model, it would stop and include that in a netlist. It worked
beautifully.

However, now that we've moved over to IC Manage, this operation in NC-
Verilog behaves strangely. It traverses the schematic hierarchy
correctly as before. However, when it detects that a verilog model
exists, rather than pulling the data from my local workspace, it tries
to pull the data from the location where it was located before we
moved over to this revision control system. I then ask the question:
what exactly tells NC-Verilog where to look for its data? How do I
tell it to look somewhere else?

Thanks,
Jake

 

Here's the sourcelink that solves the issue, for those of you who
might run across the same problem:

http://sourcelink.cadence.com/docs/db/kdb/2006/June/11252846.html

Jake