Mosis padframes

Discussion in 'Cadence' started by horridnoodle, Apr 12, 2006.

  1. horridnoodle

    horridnoodle Guest

    I am planning to fab a chip with Mosis. I have a question about their
    scalable cmos pad frames. I understand the reason behind scalable cmos
    and it provides and easy conversion between feature sizes. I downloaded
    the padframe for the AMIS C5 process, and I was wondering that since
    the layout and padframe have different layers will the Metal 1 layer
    and M1_pin layer be recognized as going together. Or is there some
    conversion that is done to insure a good layout to pin interface.

    Thanks
     
    horridnoodle, Apr 12, 2006
    #1
Ask a Question

Want to reply to this thread or ask your own question?

You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Similar Threads

  1. LEF file in mosis library?

  2. mosis pads in cadence

Loading...