Modelling an oscillator using Verilog AMS

Hello people,

I need some help. I am modelling an oscillator using verilog AMS.
The model comprises three blocks - mixer, amplifier and phase-shifter.
These modules are written at the behavioral level and instantiated in
the oscillator module.
An oscillator has feedback in it.
When I give a sine wave input to the model, it should be amplified and
then part of the output is fed back to the input using a mixer. So the
output is expected to be an increasing sine wave , growing in amplitude
in each cycle.
On the contrary the output is observed to be a constant amplitude
sinewave over all cycles.

Is it possible that all blocks try to compute their outputs at the same
time?
In such a scenario, the feedback system cannot function correctly.

Please help me debug this issue.
The code and testbench are as shown below

CODE

// Middle level high level oscillator model without any Noise //

`include "disciplines.vams"
`include "constants.vams"
`timescale 1ps / 1ps

module oscillator(out,in);
output out;
voltage out;
input in;
voltage in;
voltage vx,vref;
parameter real amplifier_gain = 15 from (-inf : inf);
parameter real test_frequency = 100k from (0 : inf);
mixer m1 (vref,in,vx);
amplifier #(.gain(amplifier_gain)) a1 (out,vref);
phase_shift #(.freq(test_frequency) , .gain1(amplifier_gain)) ps (vx,
out);
endmodule

module amplifier(out,in);
input in;
output out;
voltage in, out;
parameter real gain = 15 from (-inf : inf);
analog begin
V(out) <+ (gain * V(in));
end
endmodule

module phase_shift(out,in);
input in;
output out;
voltage in, out;
parameter real freq = 10k from (0 : inf);
parameter real resonant_freq = 60M;
parameter real beta = 0.1; //beta is a function of the circuit
components of the module and also the resonant frequency.
parameter real toff = 1.6n ;
parameter real damp = 10M;
parameter real gain1 = -6 from (-inf : inf);
parameter real sampler = 1/resonant_freq;
real flag,flag1;
real phase = `M_PI;
analog begin
@(initial_step) begin
flag1 = 0;
end
flag1 = 1;
@(timer(toff,sampler)) begin
flag = V(in);
$display("%g",flag);
end

V(out) <+ flag1*beta*V(in);

end
endmodule

module mixer(out,in1,in2);
input in1,in2;
output out;
voltage in1,in2,out;
real trial1,trial2, trial3;
analog begin

V(out) <+ (V(in1)+ V(in2));
end
endmodule



TESTBENCH

`include "constants.vams"
`include "disciplines.vams"
`timescale 10ps / 1ps
module mid_wo_noise();
wire out;
voltage in;
electrical gnd;
ground gnd;
real value;
vsource #(.type("sine"), .ampl(3m), .phase(0), .freq(60M)) v1 (in,gnd);
oscillator #(.test_frequency(60M) , .amplifier_gain(15)) osc1(out,in);
endmodule

 

This has been covered quite well at
http://www.designers-guide.org/Forum/YaBB.pl?num=1136409678

where the same question was asked.

Andrew.