Missing layer in pCell

Discussion in 'Cadence' started by stuart.duncan, Mar 24, 2009.

  1. Hi there,

    i'm missing a layout layer that should be present in a pCell when a
    given button is selected (turning on an option) on the pCell.

    So in device "nmos" there is "full_drc" button that increases the size
    of the mos (making it more robust) but it should also draw a CAD layer
    called "extra_rules" over the body of the device that will tell the
    DRC deck to enforce more stringent checks on this cell. However, the
    cell does increase in size when this button is turned on BUT the
    "extra_rules" layer does not appear.

    I've had a look in my CDS.log and there are no warnings or errors to
    give me a clue. Does anyone have any suggestions how i might trace the
    failure of this layer to be drawn? The layer "extra_rules" can be
    drawn as a polygon so its does exist.

    We are using cadence: IC5141_USR6

    Thanks

    Stu
     
    stuart.duncan, Mar 24, 2009
    #1
  2. Stuart,

    Is the layer a visible layer (i.e. is it turned on for display in the LSW)

    You could look to see what shapes are in the pcell master - with the instance
    selected, do:

    car(geGetSelSet())~>master~>shapes~>layerName

    and see if it's listed.

    Or contact customer support - that's what we're here for!

    Regards,

    Andrew.
     
    Andrew Beckett, Mar 24, 2009
    #2
  3. Hi Andrew,

    Yes, the layer is in the LSW and visible. When i do:

    car(geGetSelSet())~>master~>shapes~>layerName

    The layer in question is NOT listed. I'm in touch with cadence
    customer support so hopefully we can get to the bottom of this.
    Its a strange issue as the pdk vendor say that they do see this layer
    in a similar test case. I've logged a ticket with Cadence support.

    Thanks

    Stu
     
    stuart.duncan, Mar 24, 2009
    #3
  4. Hi Andrew, forgot to add that if you wish to e-mail me privately i can
    give you the ref' of the cadence ticket and therefore PDK vendor info.

    It's further complicated in that around 3 months ago i lay'd out a
    some of these transistors and the the offending layer was apparent,
    but now if i copy the same schematic and re-generate it, this layer
    has gone from the pCells. Unfortunately in that time we have changed a
    cadence version and probablly a few other environment settings (new
    kit and new project) so its difficult to nail down exactly when this
    change took place.

    Thanks

    Stu
     
    stuart.duncan, Mar 24, 2009
    #4
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