LVS with a schematic containing variables

I created a symbol for a certain schematic(A) containing variables
by using pPar("Wp") and so on.

In testing schematic, I did parametric sweep for the variable, "Wp".
And I got the proper Wp.

Do I have to replace pPar("Wp") with the obtained value of Wp manually
in the schematic(A) to do LVS?

When I didn't replace it, I got error in LVS because pPar("Wp") was in the
netlist of the schematic.

I am using the cadence tool.

Thank you in advance.

 

hmmm,
layouts cannot cantain variables, the dimensions are
fixed.
so, LVS will recognize there is a transistor but
will issue an error when comparing the device
parameters.
You may accept the error, knowing that the
transistor you drawn is of the right size but
if you want a successful LVS run you must
introduce a numerical value in the schematic.

one trick may help : if you do another schematic
in which you place a instance of your cell
and give the parameters a numerical value,
then LVS will not complain.
then you can have for instance a generic
inverter cell, with parameters (and no layout)
and multiple inverter layouts like inv1 inv2...

hope this helps.
stephane

 

I suspect you're doing a parametric simulation first, and then when you do an
LVS, it needs to know the default value for the parameter Wp. You would need to
set the default value of the parameter Wp in the CDF for the cell which contains
the reference pPar("Wp") - or it needs to be specified on the instance at the
level above.

There should be no need to change your pPar("Wp") references in the schematic
design for you to do LVS, provided that you define Wp somewhere...

Regards,

Andrew.