LVS question in Cadence

Hi,

I have a Cadence "schematic" view of an A/D converter (called "my_ADC")
that has std-cells supplied by a std-cell vendor instanciated (as
"symbols") in it and wired together. The std-cell vendor choose to name
his "schematic" views as "cmos_sch". Hence, the std-cell library has the
following views for each std-cell component supplied:

"cmos_sch" (i.e. actually the "schematic view", but called "cmos_sch")
"symbol" "layout" "extracted"

For my A/D converter, I have the following views:

"schematic" (that has "symbols" of the std-cells instantiated in it)
"layout" "extracted"

Now, when I do an LVS for my A/D converter (called "my_ADC") and try to
compare the "schematic" and the "extracted" of "my_ADC" it seems to
complain that it cannot find the "schematic" views for the std-cells
(since they only have a "cmos_sch" view!) during schematic netlisting.
During LVS, Cadence tries to netlist both the "extracted" view and the
"schematic" view of "my_ADC". The "extracted" view netlisting of "my_ADC"
succeeds (since the std-cells DO have an "extracted" view) but the
schematic netlisting of "my_ADC" fails (since the std-cells instanciated
inside it only have a "cmos_sch" view, and NO "schematic" view). The LVS
error messages I get from si.log are pasted at the end of this email.

There should be some way of telling LVS to look for the "cmos_sch" view
also while netlisting the "schematic" view of "my_ADC". I would imagine
this could be set in the .cdsenv or the .cdsinit files, but I am not sure
how I would do that. Could someone PLEASE help? Any inputs would be
greatly appreciated.

Thanks,
Sid

Siddharth Devarajan,
Graduate Student - ECSE Dept.,
Rensselaer Polytechnic Institute (RPI), NY,
Tel: (518)-248-7619.


I get the error shown below while running LVS for "my_ADC":
-----------------------------------------------------------

Running simulation in directory: "/home/analogkid/6hp/LVS".

Begin netlist: Jan 18 18:08:27 2005
view name list = ("auLvs" "extracted" "schematic")
stop name list = ("auLvs")
library name = "sid_test"
cell name = "my_ADC"
view name = "extracted"
globals lib = "basic"
Running Artist Flat Netlisting ...
End netlist: Jan 18 18:08:29 2005

Moving original netlist to extNetlist
Removing parasitic components from netlist
presistors removed: 0
pcapacitors removed: 0
pinductors removed: 0
pdiodes removed: 0
trans lines removed: 0
239 nodes merged into 239 nodes


Begin netlist: Jan 18 18:08:29 2005
view name list = ("auLvs" "schematic")
stop name list = ("auLvs")
library name = "sid_test"
cell name = "my_ADC"
view name = "schematic"
globals lib = "basic"
Running Artist Flat Netlisting ...
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance I8 in cellView (my_ADC
schematic) from viewlist 'auLvs schematic ' in library 'sid_test'.
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance I5 in cellView (my_ADC
schematic) from viewlist 'auLvs schematic ' in library 'sid_test'.
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
*WARNING* invalid cell view -- 0(unknown)
global error:
Cannot find switch master cell for instance I6 in cellView (my_ADC
schematic) from viewlist 'auLvs schematic ' in library 'sid_test'.
si: Netlist did not complete successfully.
End netlist: Jan 18 18:08:29 2005

Comparison program did not complete.
-------------------------------------------------------------------------

 

Set these variables in your .simrc file:

lvsSchematicViewList = '( "auLvs" "schematic" "cmos_sch" )
lvsLayoutViewList = '( "auLvs" "extracted" "schematic" "cmos_sch")
;lvsLayoutStopList = '( "auLvs" )
;lvsSchematicStopList = '( "auLvs" )

The 3rd and 4th above don't really need to be set (hence being commented out)
since the default values are already OK.

In other words you need to tell auLvs netlisting which views it is allowed to
swtich into, and in which order it should try them.

Andrew.