LVS question about layout label on internal nets

Discussion in 'Cadence' started by chen_zhitao, Nov 28, 2007.

  1. chen_zhitao

    chen_zhitao Guest

    In my previous experience, when I run LVS with Calibre, it only allows
    labels on ports in the layout. If I put a label on an internal net,
    then LVS would report error. But if I run LVS with Hercules, then it
    does not care whether there's any label on internal nets.

    Is this determined by the tool? Or are there any options that allow us
    to configure this? If there's such options, would you please show me
    how to use it?

    Thank you in advance.
     
    chen_zhitao, Nov 28, 2007
    #1
  2. chen_zhitao

    vtcad Guest

    there are options that can be set inside of the Calibre code. You can
    specify what layer Port labels are on, and what layer internal nets
    are labeled on, so it knows how to extract them.
     
    vtcad, Nov 28, 2007
    #2
  3. chen_zhitao

    chen_zhitao Guest

    there are options that can be set inside of the Calibre code. You can
    Hi, thank you. Would you please explain how to use these kind of
    options in Calibre? And how about Hercules?

    What's more, the internal net labels and port labels are usually on
    the same set of layers. So they usually cannot be identified according
    to the layer. Is there any approach to identify ports and internal
    nets on the same layer?
     
    chen_zhitao, Nov 29, 2007
    #3
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