LVS problem using Assura LVS

Discussion in 'Cadence' started by Min Pan, Aug 16, 2003.

  1. Min Pan

    Min Pan Guest

    Hello, everyone

    I had a design using standard cell. I did the P&R using Silicon
    Ensemble. Then I imported the layout from SE to icfb. I tried to use
    Assura for DRC and LVS. DRC is OK. For LVS, I think there's something
    wrong with the power/ground network. I got so many LVS mismatches, and
    they are in the following two types:

    =====================================================================[TOPLEVEL]
    ====== Shorted Instance Connections
    ===========================================
    ===============================================================================

    Layout net: avC1 shorts to:
    S U455/SUB
    S U455/LVSS
    Layout net: avC1 shorts to:
    S U456/SUB
    S U456/LVSS
    Layout net: avC1 shorts to:
    S U457/SUB
    S U457/LVSS
    .......

    =====================================================================[TOPLEVEL]
    ====== Unmatched Internal Nets
    ================================================
    ===============================================================================

    S ?_unconnected2
    S ?_unconnected3
    S ?_unconnected4
    .......


    All of them seems related to the power/ground network. I use the
    verilog netlist for my design and cdl file for standard cell as the
    LVS input netlist. What may be the cause of this problem? Any help is
    appreciated.

    Thanks.

    Min Pan
    e-mail:
     
    Min Pan, Aug 16, 2003
    #1
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