lvs flat mode problem

Hi all,
I am using diva Lvs to perform flat lvs. The problem facing now is
the layout netlister also netlists the filler and endcap cell. They
have been defined as "ivCellType graphic", "nlAction ignore",
lvsIgnore t" already. Is there anythings else I need to define? My
viewlist are as follow.....

lvsSchematicViewList = '( "auLvs" "schematic" "gate_sch" "cmos_sch" )
lvsLayoutViewList = '( "auLvs" "extracted" "schematic" "gate_sch"
"cmos_sch" )
lvsSchematicStopList = '( "auLvs" )
lvsLayoutStopList = '( "auLvs" )

by the way, my schematic is imported from verilog. Is it a source of
problem? Thanks in advance...

tnk

 

Since you say you are doing flat LVS, I assume you mean you did a flat
extract, then run LVS. There is no hierarchical LVS in Diva.

Flat extraction ignores the ivCellType property since that property is
only used during macrocell extraction. The property controls whether
macrocell extraction expands the cell instance into shapes for
processing (graphic) or treats the instance as a device (macro).

If your filler and endcap cells have devices in them, you should have
corresponding devices in the schematic, which would make LVS happy. If
you want to ignore the cells, you can do this with an ivIncludeValue
property on the master and setting the inclusion limit with the -inc
ivVerify command or on the Extract form.

Be aware that any interconnect provided by the filler and endcap will
not be seen. The ivIncludeValue literally controls whether the cell is
included in the extraction or not. There is no way to tell the tool to
process the shapes of a cell, but not to netlist any devices it finds in
the cell.

 

What you were assuming is correct. I did the flat extract. It is not
that I don't want them to be extracted. Just that the LVS keep on
complaining that there is no matching device in schematic. And also
some odd errors like vdd! and gnd! nets and terminals can't be matched
on both layout and schematic. Are you saying that I need to draw empty
boxes in the schematic and name them as filler and endcap?

tnk

 

Not an empty box, but the circuit that is in the filer and endcap. If
you did a flat extraction, all that should have come from there are
basic devices like transistors, resistors and such. Those same devices
should be in the schematic.

If LVS is complaining about higher level cell names, then you it sounds
like you did a macrocell extraction. That would be the only way the
filler and endcap cells should appear in the LVS netlist.

Either way, you have to have matching devices in the both the schematic
and the layout to be LVS clean.