LVS CADENCE

Discussion in 'Cadence' started by abdmouleh.med, Oct 17, 2007.

  1. abdmouleh.med

    abdmouleh.med Guest

    hello,

    I made the LVS buffer stage but I don't understand the LVS/si.out
    result :

    layout
    schematic
    instances
    un-matched 5 1
    rewired 2 0
    nets
    un-matched 6 5
    merged 0 1
    terminals
    un-matched 0 0
    total 0 9

    and I didn't understand "rewired" and "merged"..

    thank you for your help.
     
    abdmouleh.med, Oct 17, 2007
    #1
  2. abdmouleh.med

    The Master Guest

    Rewire basically means that the LVS is dirty, and it's trying to work out
    what the correct hook-up should be. I never found the feature useful in
    Diva LVS (it is VERY helpful in Assura though).

    Whenever I personally run Diva LVS, I turn the rewire option off. Half
    way down the LVS form, under "LVS options".

    Now, it won't try to figure out why it's wrong, it will just report what
    is wrong.
     
    The Master, Oct 18, 2007
    #2
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