LVS and verification

Discussion in 'Cadence' started by weidongl, Apr 2, 2004.

  1. weidongl

    weidongl Guest

    Hi, all:

    Building up a chip with both custom block and standard cell in SE, some
    questions about the LVS and verification of the circuit.

    1. What is the tool to make LVS? Traditional LVS could not be applied
    since we haven't detail layout info on the standard cells.

    2. Verification of the chip. What is the proper tool(s) to verify the
    timing and functionality of the circuit? Is LDV is good option?

    Any suggestions are welcome. Thanks in advance!

    /Weidong
     
    weidongl, Apr 2, 2004
    #1
  2. weidongl

    Diva Physical Verification Guest

    You can use Diva macrocell extraction to get the standard cells as
    primitive elements in the extracted view. The LVS can compare the
    netlists at the standard cell level. This assumes the standard cells
    have been properly built with the ivCellType property set to macro, and
    NLP expression properties needed by the OSS netlister. I would be
    surprised if the library vendor had not done this already.
     
    Diva Physical Verification, Apr 3, 2004
    #2
  3. weidongl

    S. Badel Guest

    I know Assura also has capability to do macro-cell lvs. They call
    it blackBox however in the documentation. If you already have assura
    rules it'll probably be easier, provided your abstract cells contains
    df2 pins (that should probably be the case).
    have a look at assura doc if interested.

    stéphane
     
    S. Badel, Apr 5, 2004
    #3
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