Looking for Veriloga lint program

Discussion in 'Cadence' started by DReynolds, Aug 24, 2006.

  1. DReynolds

    DReynolds Guest

    Can anyone tell me how to check my veriloga for good style using a lint
    type program? I searched this board and did a quick google, but did not
    find anything that looked like a veriloga lint.

    I recently had this code that did not do what I thought it would do:

    generate i(0,5,+1) begin
    code =code + (V(address >vth) ? pow2 : 0;
    end

    I was expecting it to take my address and turn it into a number, but it
    didn't. It always gave 32 as an answer.

    Adding a set of paren fixed it:
    code =code + ((V(address >vth) ? pow2 : 0);

    The original did compile and run so I was hoping lint could find an
    error like this....

    David Reynolds
     
    DReynolds, Aug 24, 2006
    #1


  2. In this very particular case, I would say that if verilog would have
    supported the += operator you would never discover that the ternary
    operator has the lowest precedence of all operators. Would a linter see
    this as a possible error? How about all those cases where this
    behaviour is intended? Your ternary itself is no problem, I see loads
    of code where the parenthesis are not there (because the ternary has
    lowest precedence anyway) so you have even less control on what belongs
    where.

    In the skill ref and user manual they say that you have to be careful
    to enforce proper precedence with parenthesis. Maybe that should be
    done explicitely in the Verilog-A manual also, maybe by using this as
    an example.

    But, no, I don't know of any linter. Do you guys usually use linters?
    If so, shouldn't that be a responsibility of Cadence?
     
    Svenn Bjerkem, Aug 25, 2006
    #2


  3. Well, a syntax check is being done when you close the cellView after editing it.
    It's not a lint as such.

    Anyway, I don't think this example would be caught by a lint, because you can't
    tell that it wasn't intended. If you omit the parentheses and don't know the
    precedence of each operator, then it will do other than you want if you get it
    wrong!

    Of course it would be a reasonable enhancement request for Cadence to provide a
    linting tool for Verilog-A(MS), but not sure that it is necessarily a
    "responsibility"?

    Regards,

    Andrew.
     
    Andrew Beckett, Aug 30, 2006
    #3
  4. DReynolds

    DReynolds Guest

    Andrew, I was looking at it from a different point of view... verilog
    has a whole eco system of lint programs to try and help people make
    good models... and these are supposed to be professional code writers!
    Looking at veriloga, which I would claim is used more by people who
    don't code for a living so a lint tool would be even more valuable to
    them.

    Sounds like an opportunity to me...

    David

     
    DReynolds, Aug 30, 2006
    #4
  5. It does sound like an opportunity. Not speaking for Cadence here, but I guess
    the trouble is that people would pay an independent company for such a lint
    program, but would expect Cadence to give it away... (strange that, isn't it?).

    Andrew.
     
    Andrew Beckett, Aug 30, 2006
    #5
  6. DReynolds

    jdvontass Guest

    Might be an opportunity for an Open source team..
    Could be written as a stand alone tool, and then integrated into Nedit,
    vim, eemacs.
    OTOH Thats the kind of mistake each of us makes only twice..
    Don't want this to be TOO easy to do!
    :D
     
    jdvontass, Sep 2, 2006
    #6
  7. I would call it one of those little utilities that makes a difference.
    That won't justify a 20% increase in license fee but it would probably
    make an engineer more comfortable with his Cadence toolchest. And we
    all know a happy user is a happy user.
     
    Svenn Bjerkem, Sep 6, 2006
    #7
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