Logic Depth Dependent Synthesis

Greetings all EDA experts and developers,

Any tool from Synopsys/Cadence/Mentor/Magma suit of tools that would
allow a "logic-depth dependent"
synthesis?

I want to fix my logic depth to 10 and only 10 (that is my
"constraint"). Can I synthesize a given netlist (not necessarily 10
levels of logic) to one with exactly 10?

Regards,

Hrh.

 

Maybe. For example, you could give your favorite synthesis tool a
cell library where every cell has unit delay, there is no wire delay,
and you set your delay constraint to 10. That would do it in theory,
but there is no guarantee that the heuristics used will be at all
well-tuned to that kind of library. For example, a tool might waste
a lot of time trying to do gate sizing to improve the timing, without
realizing that it makes absolutely no difference for that library.

Perhaps you should first ask why you want to achieve this particular
constraint. The answer may guide you in your choice of tool.