Lithography simulation

Hello,

Does anyone know how to run lithography simulation after layout? It is
said this would improve yield. Currently in our group, we have Calibre
Litho-Friendly Design package (LFD) for this purpose, but we don't
have the lithography simulation rule file. Is the lithography rule
file provided by the foundry or the same as DRC file?

Thanks and looking forward to your reply.

Regards,

Mobil

 

Dear Mobile,

Calibre LFD is a great tool but it is as good as a chocolate tee pot
without an LFD Deck from your foundry. You definitely need this
'precious' file to run LFD.
Who told you LDF improves Yield BTW ? There is a bit of marketing hype
in there I'm afraid ...
LFD is great tool that spots the areas in your layout that are most
likely to fail during lithography. LFD allows you to improve your
layout to make it better lithography wise. And off the top of my head,
LFD allows a KOF accurate extraction of device properties (ex: MOS W/
L) when you run PEX. In other words, if you draw a MOS whose W/L are
2/1, then LFD may come with something like 1.95/0.99 (Just an
example), which should be the true value on the silicon.
Again, LFD is just an engine that should be fueled with the yield data
from your foundry. The results are really depending on how the models
are fitting the reality of Yield on the real silicon. That's the
hardest part of the Job in fact.

At the end, the magic EDA tool that makes your yield going up is an
utopia I'm afraid, the silicon world is far from being as ideal as
some 'marketing' guys though it. I have very very good reasons in
saying this but I'm not going any further so far. I can tell more on
request though ;-)

Enjoy yourself !

Riad.

 

Thank you very much for your long letter, Riad.
Actually in our university project, we mostly deal with the RF circuit
which only contains a few number of wires unlike the large-scale
digital circuits. I think you're right, doubling the vias is a good
way in most of scenarios.

Thanks a lot.

Regards,

Mobil